1. Field of the Invention
The present invention relates to a function generator used as a random access memory (RAM), and in particular to a function generator having a synchronous, dual port RAM capability.
2. Description of the Related Art
Static random access memory (hereinafter RAM) is well known in the art. A RAM has two fundamental operating modes: a read mode and a write mode. In a read mode, a write enable input signal is inactive, wherein the RAM operates as a read only memory (ROM), i.e. the data stored by the RAM cannot be changed. In this mode, the data stored at the RAM cell location defined by the address inputs is provided as an output signal.
In a write mode, the write enable input signal is active, thereby allowing data to be written into the RAM cell location specified by the address lines. However, the timing of this operation is critical to ensure that the data is written to only the specified RAM cell location and that other cell locations are left undisturbed. Specifically referring to FIG. 1, write cycle 105 is initiated by a falling edge of system clock signal 101. The active (i.e logic one) write enable (WE) signal 104 is not asserted until shortly after the address signals 102 are stable. The active WE signal 104 must last for at least a specified minimum time period 106. Additionally, address signals 102 must stay constant during and preferably even for a specified hold time beyond the end of active WE signal 104. Data signal 103 must also be constant for a specified time before the end of active WE signal 104, as well as for a predetermined time after the end of active WE signal 104. If any of these requirements are violated, the data may not be written properly into the desired RAM location, and/or it may be written into an undesired location.
FIG. 2 illustrates one portion of a configurable logic block (CLB) including two function generators 201 and 202 (also commonly referred to as F and G function generators, respectively). Function generators are typically implemented using look-up tables (LUTs), which in turn typically comprise a plurality of RAM cells. The use of RAM for function generators is described in further detail in U.S. Pat. No. Reissue 34,363, reissued on Aug. 31, 1993, which is incorporated by reference in its entirety. In the embodiment shown in FIG. 2, each function generator comprises a 16.times.1 LUT. Four CLB input signals F1-F4 determine which of the sixteen stored RAM values is provided on output line F'. In a similar manner, four CLB input signals G1-G4 determine which of the sixteen stored RAM values is provided on output line G'.
Control signals C1-C4 can each generate any one of four logic signals. In FIG. 2, these four logic signals include: enable clock (EC), write enable (WE), a first data signal (DIN), and a second data signal (H1). The WE signal is provided to both AND gates 209 and 211. If the WE signal is low (i.e. inactive), then function generators 201 and 202 perform as typical CLB function generators (i.e. having only ROM capability). However, if the WE signal is high (i.e. active), then both function generators 201 and 202 will be written to assuming other preconditions are met. For example, memory cells 203 and 204 determine whether one of or both of function generators 201 and 202 fail to receive the active WE signal. For example, if memory cell 204 stores a logic low signal, then function generator 201 is disabled for write access and performs only as a ROM. Thus, memory cells 203 and 204 provide an additional means for RAM write deselection. However, even if both of the above-described enabling conditions are met, memory cell 205 and data signal Hi may disable the RAM write functionality of one of function generators 201 and 202.
Memory cell 205 provides two functions. First, a predetermined logic state stored in memory cell 205 controls multiplexer 207, thereby determining whether function generators 201 and 202 are configured as two 16.times.1 RAMs with two data inputs and two data outputs (i.e. function generator 202 receiving data signal Hi and function generator 201 receiving data signal DIN) or as one 32.times.1 RAM with one data input (i.e. function generators 201 and 202 both receiving data signal DIN). Note that additional circuitry, i.e. a multiplexer (not shown), determines which output line (line F' or line G') provides the output signal for the 32.times.1 RAM.
Second, that predetermined logic state is also provided to 0R gates 208 and 210. If that predetermined logic state is high (and assuming signal WE is high and memory cells 203/204 store logic high signals), the RAM write capability of function generators 201 and 202 is enabled. In this configuration, function generator 202 is written with data signal H1 and function generator 201 is written with data signal DIN (a 16.times.2 configuration). On the other hand, if that predetermined logic state of memory cell 205 is low, data signal HI determines which of function generators 201 and 202 provides the RAM write capability. In other words, data signal H1 functions as another address signal for the 32.times.1 RAM.
Referring to FIGS. 1 and 2, assuming that the high portion of system clock signal 101 is used to generate write enable signal WE, when system clock signal 101 goes low, write enable signal WE must go low. Additionally, the new address and data signals for the following cycle must be generated. However, the speed associated with each of these operations may vary. For example, if the speed to generate a new address is faster than the speed to turn off the write enable signal WE, then the timing requirements of the system are violated. As previously noted, if any of the timing requirements are violated, the data may not be written properly into the desired RAM location, and/or it may be written into an undesired location.
To ensure that a data signal is written to only the specified location and that other cell locations are left undisturbed, the user usually must wait one clock cycle before another write cycle 105 can begin, i.e. to generate a new address. The 1994 Xilinx Data Book, which is incorporated by reference in its entirety, describes one solution to this problem on pages 8-139 through 8-147. In this solution, a global clock is used as a write enable signal. However, in this solution, every cycle is a write cycle, thereby requiring a read output signal (i.g. the output signal of function generator 201 or 202 when the function generator acts as a ROM) to be fed back to its data input terminal to write the old data when a write cycle is undesired. This feedback operation necessitates the use of flip-flops and a multiplexer which significantly increases the required logic. Moreover, the address is generated by the falling clock edge, leaving only the clock low time to generate and route the address and accommodate the data set-up time. Thus, the above-described solution sacrifices density and speed to achieve reliable performance.
Therefore, a need arises for a logic circuit which eliminates the above-described time delays without increasing the required logic cost.